1. Field of the Invention
The present invention relates to circuits having testing function circuits and, more specifically, to a circuit incorporating a testing circuit for testing each of the circuit portions constituting a data processing circuit.
2. Description of the Prior Art
As the design of circuits such as LSI becomes more and more complicated, the testing thereof also becomes complicated. Sometimes a test circuit is incorporated between circuit portions constituting the circuit so as to enable appropriate testing of each the of circuit portions one by one.
FIG. 1 is a conventional testing circuit of scan register type incorporated between circuit portions for testing each of the circuit portions.
In testing, the testing circuit inputs test data to a desired circuit portion, and outputs data processed by the exact portion to verify the output data. When it does not test the circuit portion, the whole circuit constituted by a plurality of circuit portions operates normally.
Referring to the figure, the circuit portions 1a, 2a, and 3a constituting the circuit are, for example, combinational logic circuits having n input terminals 11, 21 and 31 and n output terminals 12, 22 and 32, respectively.
The testing circuit comprises n scan latch circuits 9.sub.1 .about.9.sub.n arranged between the first circuit portion 1a and the second circuit portion 2a, and n scan latch circuits 9.sub.n+1 .about.9.sub.2n arranged between the second circuit portion 2a and the third circuit portion 3a. Each of the scan latch circuits 9.sub.1.about. 9.sub.2n has a first input terminal a, a second input terminal b, a control terminal c and an output terminal d. A signal inputted to the first input terminal a or a signal inputted to the second input terminal b is selectively outputted to the output terminal d in correspondence with a control signal C inputted to the control terminal c.
FIG. 2 is a schematic diagram showing a structure of a general scan latch circuit, which is applied to the scan latch circuits 9.sub.1 .about.9.sub.n of FIG. 1.
The scan latch circuit is constituted by a multiplexer 7 comprising an inverter 4 and two transmission gates 5 and 6, and a latch circuit 8. In the multiplexer 7, when the control signal C inputted to the control terminal c is at "L" level, the transmission gate 5 is on and the transmission gate 6 is off. Consequently, the signal DI.sub.2 inputted to the first input terminal a is transferred to the latch circuit 8. Meanwhile, when the control signal C is at "H" level, the transmission gate 5 is off and the transmission gate 6 is on. Consequently, the signal DI.sub.2 inputted to the second input terminal b is transferred to the latch circuit 8.
The latch circuit 8 is a master-slave type latch circuit in synchronization with a clock signal .phi. which takes in the data DI from the multiplexer 7 when the clock signal .phi. is at the "H" level and outputs and holds the data DI when the clock signal .phi. is at the "L" level. Namely, the scan latch circuit takes in the signal DI.sub.1 inputted to the first input terminal a when the control signal C is at the "L" level. When the control signal C is at the "H" level, it takes in the signal DI.sub.2 inputted to the first input terminal b.
In FIG. 1, the first input terminals a of the scan latch circuits 9.sub.l .about.9.sub.n of the first to n th stages are respectively connected to the output terminals 12 of the first circuit portion 1a. The output terminals d are connected to the input terminals 21 of the second circuit portion 2a and to the second input terminals b of the scan latch circuits 9.sub.2 .about.9.sub.n+1 of the succeeding stage, respectively.
The first input terminals a of the scan latch circuits 9.sub.n+1 .about.9.sub.2n of the (n+1)th to 2n th stages are respectively connected to output terminals 22 of the second circuit portion 2a. The output terminals d are respectively connected to input terminals 31 of third circuit portion 3a. The output terminals d of the scan latch circuits 9.sub.n+1 .about.9.sub.2n-1 of the (n+1)th .about.(2n-1)th stages are respectively connected to the second input terminals b of the can latch circuits 9.sub.n+2 .about.9.sub.2n of the succeeding stage, respectively.
The control terminals c of all scan latch circuits 9.sub.1 .about.9.sub.2n are connected together to receive the control signal C. The input terminals 11 of the first circuit portion 1a are respectively connected to the data input terminals I.sub.1 .about.I.sub.n. The output terminals 32 of the circuit portion 3a are respectively connected to data output terminals O.sub.1 .about.O.sub.n.
In the following the operation of the testing circuit will be described.
The operation of the testing circuit can be divided into the operation mode in which the control signal C is at the "L" level, and the shift mode in which the control signal C is at the "H" level.
In the operation mode, all scan latch circuits 9.sub.1 .about.O.sub.2n are adapted to take in the signal inputted to first input terminals a. Therefore, the data inputted in parallel from the data input terminals I.sub.1 .about.I.sub.n are inputted to the first circuit portion 1a, and the data processed in the first circuit portion 1a are transferred to the second circuit portion 2a through the scan latch circuit 9.sub.1 .about.9.sub.n. The data processed in the second circuit portion 2a are transferred to the third circuit portion 3a through the scan latch circuits 9.sub.2n .about.9.sub.n+1, and the data processed in the circuit portion 3a are outputted in parallel from the data output terminals O.sub.1.about. O.sub.n. Namely, in the operation mode, the whole data processing circuit constituted by the circuit portions 1a, 2a and 3a carries out normal data processing successively in synchronization with the clock signal .phi..
In the shift mode, all scan latch circuits 9.sub.1 .about.9.sub.2n are adapted to take in signals inputted to the second input terminals b, so that the scan latch circuits 9.sub.1 .about.9.sub.2n constitute one shift register. Therefore, the serial data SI inputted to the second input terminal of the scan latch circuit 9.sub.1 of the first stage is successively shifted to the scan latch circuits 9.sub.2.about. 9.sub.2n of the succeeding stages in synchronization with the clock signal .phi. to be outputted from the output terminal d of the scan latch circuit 9.sub.2n of the last stage as an output data SO. By combining these two operations, the circuit portions can be tested one by one.
In the following, the test of the second circuit portion 2a will be described as an example.
First, the test circuit is set at the shift mode by setting the control signal C at the "H" level. Test data for testing the second circuit portion 2a are serially inputted from the second input terminal b of the scan latch circuit 9.sub.1 of the first stage to be stored in the scan latch circuits 9.sub.1.about. 9n of the first to n th stages. Thereafter, by setting the control signal C at "L" level, the test circuit is drawn into the operation mode, and the output data of the test data processed by the second circuit portion 2a are taken in to the scan latch circuits 9.sub.n+1 .about.9.sub.2n of the (n+1)th.about.2n th stages. Thereafter, the testing circuit is again switched to the shift mode, and the data held in scan latch circuits 9.sub.n+1 .about.9.sub.2n are serially outputted to the outside from the output terminal d of the scan latch circuit 9.sub.2n of the last stage by shifting operation to verify the data.
In the above described conventional testing circuit, the test data for testing each circuit portion must be serially inputted, and the data processed in each circuit portion must be serially taken out. Therefore, the test requires long periods of time, and it is difficult to prepare the test data.